IBM Alliance Partners 'Open For Business' for 32 nm High-k/Metal Gate Designs

David Lammers, News Editor -- Semiconductor International, 4/14/2008 10:48:00 AM

IBM Corp. (Armonk, N.Y.) and its partners are “open for business” for early customer design engagements using a bulk 32 nm technology with a high-k/metal gate stack, said Gary Patton, an IBM vice president. IBM announced today that a low-power 32 nm design enablement package is now available, with a design prototyping shuttle starting in the third quarter of 2008 and continuing on a quarterly schedule.

Patton said the partners believe the use of a high-k/metal gate technology will provide cost, performance and power savings. “Using high-k/metal gate technology means that we can shrink the gates and the space between the gates, enabling better scaling than if we had used a poly/oxynitride gate stack. We can push the contact size and improve the overlay between the contact and the gate.”

Patton said foundries such as Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) that do not plan to use a high-k/metal gate technology at the 32 nm generation will need to use a costly triple oxide technology, with a thin gate oxide for the high-performance logic circuits and a thick oxide to prevent leakage in the SRAM arrays. TSMC described its process last December.

Also, he said other foundries will need to do “significant strain engineering” on “zero-degree unrotated wafers” to provide a performance gain at 32 nm design rules.

Patton said avoiding those complexities will make the alliance's high-k/metal gate process cost-competitive as a mainstream foundry process. He added that the Common Platform’s early customers are expected to be in the cost-sensitive portable and wireless handset space.

The partners, including Chartered Semiconductor Manufacturing Ltd. (Singapore), Freescale Semiconductor Inc. (Austin, Texas), Infineon Technologies AG (Munich), Samsung Electronics Co. Ltd. (Seoul, South Korea), STMicroelectronics (Geneva) and Toshiba Corp. (Tokyo), are developing the 32 nm process at IBM’s Semiconductor Research and Development Center in East Fishkill, N.Y.

The alliance partners often take the standard process and tweak it for their own customer’s requirements. For the commercial foundry market, the Common Platform foundry partners — IBM, Chartered and Samsung — offer compatible processes that allow for second-source capabilities. Patton said the Common Platform partners are the first in the foundry industry to offer a 32 nm high-k/metal gate technology.

He said the 32 nm test circuits show a 35% performance improvement compared with 45 nm circuits at the same operating voltage. Power reduction can be as much as 30-50% depending on the operating voltage. Also, the high-k/metal gate technology — as tested on product library test chips and industry standard microprocessor critical paths — provided up to 40% performance improvements over conventional poly/SiON gate technology at the same technology dimensions.

Patton said the 32 nm technology was designed to be extendable to a half-node 28 nm generation without increasing the number of layers, which use double etch, double exposure lithography.

Also, he said work conducted at the College of Nanoscale Science and Engineering’s Albany NanoTech Complex shows that the 32 nm process can be extended to the 22 nm generation.

Some customers will skip the 45 nm generation and move directly to 32 nm to take advantage of the high-k/metal gate process. Others now designed in at 45 nm will skip the 40 nm shrink, which the Common Platform partners will offer and move to 32 nm design rules, he added.

The design enablement kit includes the transistors models, design rule checker, and other basic intellectual property (IP). Large customers and commercial library vendors can proceed to develop gate-level libraries and circuits. Early production of 32 nm products is expected in the second half of 2009, Patton said. A video describing IBM's 32 nm technology can be seen here.

Last December, the alliance partners announced a test 32 nm SRAM with a cell size of .15 µm².

In a statement, Dirk Wrister, director of process technology at Freescale, said, “This early design and modeling work indicates that the high-k/metal gate technology is going to deliver a significant product and performance differentiation. These early results are a significant step in the demonstration of high-k/metal gate viability in 32nm technology.”

Intel (Santa Clara, Calif.) spokeswoman Kari Aakre said that last September at the Intel Developer Forum, the company announced a fully functional 32 nm SRAM plus a logic test chip in a package with more than 1.9 billion transistors.

“Intel is on track to ramp 32 nm logic technology in 2009,” she said.